The embodiments herein relate to the design of via chains and serpentine/comb testable structures, and more specifically, to structures and methods that save time and are less destructive when testing via structures.
An integrated circuit (IC) is a semiconductor device containing many small, interconnected components such as diodes, transistors, resistors, and capacitors. These components function together to enable the IC to perform a task, such as control an electronic device or perform logic operations. ICs are found in computers, calculators, cellular telephones, and many other electronic devices.
ICs and other semiconductor devices are fabricated on small rectangles, known as “dies,” which are filled with multiple layers of the components, such as transistors, resistors, and capacitors, during the fabrication process. The connections between the layers are known as vias. A via is a metal interconnect coupled between two planar conductive layers in a semiconductor die. Multiple vias may be coupled together in what may be referred to as a “via chain” connecting one conductive region in an IC to another conductive region.
A manufacturing error in one of the components mentioned above may render an IC or semiconductor device incapable of functioning properly. For example, consider a memory device containing several ICs. If a transistor within one of the ICs fails to function properly, the memory device may produce memory errors. Vias are also subject to manufacturing errors. When a manufacturing error occurs in a via, the via may not conduct properly and thus may prohibit an IC from functioning correctly. For instance, an open via or a partially open via may prohibit a device from functioning as designed. An open via may have a high or infinite resistance, and a partially open via may have a higher than average resistance. Therefore, testing via structures is a fundamental aspect of IC production. The embodiments also relate to in-plane structures as well.